SMT Dictionary – Surface Mount Technology

SMT Dictionary – Surface Mount Technology Acronym and Abbreviation

SMT (Surface Mount Technology) is a packaging technology in electronics that mounts electronic components on the surface of a Printed Circuit Board / Printed Wiring Board (PCB / PWB) instead of inserting them through holes of the board. SMT or Surface Mount Technology is relatively new technology in electronicsand provides state-of-art, miniature electronics products at reduced weight, volume and cost. History of SMT is rooted in the technology of Flat Packs (FP) and hybrids of 1950s and 1960s. But for all practical purposes, today’s SMT can be considered

to be a continually evolving technology. Currently the use of Fine Pitch, Ultra Fine Pitch (UFP) and Ball Grid Arrays (BGAs) are becoming even more common.

Even the next level of packaging technologies such as Chip-on-Board (COB), Tape-Automated Bonding (TAB), and Flip Chip Technologies are gaining widespread acceptance. Multichip Modules (MCMs) using wire bond, TAB, or Flip Chip are used to achieve the highest performance possible but with a cost premium.

SMT Dictionary

  1. A-Stage: The condition of low molecular weight of a resin polymer during which the resin is readily soluble and fusible.
  2. Anisotropic: A material fillet with a low concentration of large conductive particles designed to conduct electricity in the Z axis but not the X or Y axis. Also called Z axis adhesive.
  3. Annular Ring: The conductive material around a drilled hole.
  4. Aqueous Cleaning: A water-based cleaning methodology which may include the addition of the following chemicals: neutralizers, saponifiers, and surfactants. May also use DI (Deionized) water only.
  5. Aspect Ratio: A ratio of the thickness of the board to its preplated diameter. A via hole with aspect ratio greater than 3 may be susceptible to cracking.
  6. Azeotrope: A blend of two or more polar and non polar solvents that behaves as a single solvent or remove polar and nonpolar contaminants. It has one boiling point like any other single component solvent, but it boils at a lower temperature than either of its constituents. The constituents of the azeotrope cannot be separated.
  7. B. Stage: Sheet material (e.g., glass fabric) impregnated with a resin cured to an intermediate stage.
  8. Ball Grid Array (BGA): Integrated circuit package in which the input and output points are solder balls arranged in a grid pattern.
  9. Blind Via: A via extended from an inner layer to the surface.
  10. Blowhole: A large void in a solder connection created by rapid outgassing during the soldering process.
  11. Bridge: Solder that bridges across two conductors that should not be electrically connected, thus causing an electrical short.
  12. Buried Via: A via hole connecting internal layers that does not extend to the board surface.
  13. Butt Joint: A surface mount device lead that is sheared, so that the end of the leads contacts the board and land pattern.
  14. C-Stage Resin: A resin in a final stage of cure.
  15. Capillary Action: The combination of force, adhesion, and cohesion which causes liquids such as molten metal to flow between closely spaced solid surfaces against the force of gravity.
  16. Castellation: Metallized semicircular radial features on the edges of LCCC’s that interconnect conducting surfaces. Castellations are typically found on four edges of a leadless chip carrier. Each lies within the termination area for direct attachment to the land patterns.
  17. CFC: Chlorinated fluorocarbon, cause depletion of ozone layer and scheduled for restricted use by the environmental protection agency. CFC’s are used in air conditioning, foam insulation and solvents, etc.
  18. Characteristic Impedance: The voltage-to-current ratio in a propagation wave, i.e., the impedance which is offered to the wave at any point of the line. In printed wiring its value depends on the width of the conductor to ground plane(s) and the dielectric constant to the media between them.
  19. Chip Component: Generic term for any two-terminal leadless surface mount passive devices, such as resistors and capacitors.
  20. Chip-on-Board Technology: Generic term for any component assembly technology in which an unpackaged silicon die is mounted directly on the printed wiring board. Connections to the board can be made by wire bonding, tape automated bonding (TAB), or flip-chip bonding.
  21. CLCC: Ceramic leaded chip carrier.
  22. Cold Solder Joint: A solder connection exhibiting poor wetting and a grayish, porous appearance due to insufficient heat or excessive impurities in the solder.
  23. Column Grid Array (CGA): Integrated Circuit (IC) package in which the input and output points are high temperature solder cylinders or columns arranged in a grid pattern.
  24. Component Side: A term used in through-hole technology to indicate the component side of the PWB.
  25. Condensation Inert Heating: A general term referring to condensation heating where the part to be heated is submerged into a hot, relatively oxygen-free vapor. The part, being cooler than the vapor, causes the vapor to condense on the part transferring its latent heat of vaporization to the part. Also known as vapor phase soldering.
  26. Constraining Core Substrate: A composite printed wiring board consisting of epoxy-glass layers bound to a low thermal-expansion core material, such as copper-incar-copper, graphite-epoxy, and aramid fiber-epoxy. The core constrains the expansion of the outer layers to match the expansion coefficient of ceramic chip carriers.
  27. Contact Angle: The angle of wetting between the solder fillet and the termination or land pattern. A contact angle is measured by constructing a line tangent to the solder fillet that passes through a point of origin located at the place of intersection between the solder fillet and termination or land pattern. Contact angles of less than 90 Degrees Celsius (Positive wetting angles) are acceptable. Contact angles less than 90 Degree Celsius (Negative wetting angles) are unacceptable.
  28. Control Chart: A chart that tracts process performance over time. Trends in chart are used to identify process problems that may require corrective action to bring the process under control.
  29. Coplanarity: The maximum distance between the lowest and the highest pin when the package rests on a perfectly flat surface. 0.004 inch maximum Coplanarity is acceptable for peripheral packages and 0.008 inch maximum for BGA.
  30. Crazing: An internal condition that occurs in the laminated base material in which the glass fibers are separated from the resin at the weave intersections. This condition manifests itself in the form of connected white spots, of “cross,” below the surface of the base material, and is usually related to mechanically induced stress.
  31. CTE (Coefficient of Thermal Expansion): The ratio of the change in dimensions to a unit change in temperature. CTE is commonly expressed in ppm/ degree Celsius.
  32. Delamination: A separation between plies within the base material, or between the base material and the conductive foil, or both.
  33. Dentritic Growth: Metallic filament growth between conductors in the presence of condensed moisture and electrical bias. (Also known as “whiskers.”)
  34. Design for Manufacturability: Designing a product to be produced in the most efficient manner possible in terms of time, money, and resources taking into consideration how the product will be produced, utilizing the existing skill base (and avoiding the learning curve) to achieve the highest yields possible.
  35. Dewetting: A condition that occurs when molten solder has coated a surface and then receded, leaving irregularly shaped mounds of solder separated by areas covered with a thin solder film. Voids may also be seen in the dewetted areas. Dewetting is difficult to identify since solder can be wetted at some locations and base metal may be exposed at other locations.
  36. Dielectric Constant: A property that is a measure of a material’s ability to store electrical energy.
  37. DIP (Dual In-Line Package): A package intended for through-hole mounting that has two rows of leads extending at right angles from the base with standard spacing between leads and row.
  38. Disturbed Solder Joint: A condition that results from motion between the joined members during solder appearance, although they may also appear lustrous.
  39. Drawbridging: A solder open condition during reflow in which chip resistors and capacitor resemble a draw bridge.
  40. Dual-Wave Soldering: A wave soldering process that uses a turbulent wave with a subsequent laminar wave. The turbulent wave ensures complete solder coverage in tight areas and the laminar wave removes bridges and icicles. Designed for soldering surface mount devices glued to the button of the board.
  41. Electroless Copper: Copper plating deposited from a plating solution as a result of a chemical reaction and without the application of an electrical current.
  42. Electrolytic Copper: Copper plating deposited from a plating solution by the application of an electrical current.
  43. Etchback: The controlled removal of all components of base material by a chemical process on the side walls of holes in order to expose additional internal conductor areas.
  44. Eutectic: The alloy of two or more metals that has a lower melting point than either of its constituents. Eutectic alloys, when heated, transform directly from a solid to a liquid and do not show pasty regions.
  45. Fiducial: A geometric shape incorporated in the artwork of a printed wiring board, and used by a vision system to identify the exact artwork location and orientation. Generally three fiducial marks are used per board. Fiducial marks are necessary for the accurate placement of fine pitch packages. Both global and local fiducials can be used. Global fiducials (generally three) locate the overall circuitry pattern to the PCB, whereas local fiducials (one or two) are used at component locations, typically fine pitch patterns, to increase the placement accuracy. Also known as alignment target.
  46. Fillet: (1) A radius or curvature imparted to inside meeting surfaces. (2) The concave junction formed by the solder between the footprint pad and the SMC lead or pad.
  47. Fine Pitch: A center to center lead distance of surface mount packages of 0.025 inch or less.
  48. Flatpack: An integrated circuit package with gull wing or flat leads on two or four sides, with standard spacing between leads. Commonly the leads pitches are at 50 mil centers, but lower pitches may also be used. The packages with lower pitches are generally referred to as fine pitch packages.
  49. Flip-Chip Technology: A chip-on-board technology is which the silicon die is inverted and mounted directly to the printed wiring board. Solder is deposited on the bonding pads in vacuum. When inverted, they make contact with the corresponding board lands and the die rests directly above the board surface. It provides the ultimate is densification also known as C4 (controlled collapse chip connection).
  50. Footprint: A nonpreferred term for Land Pattern.
  51. Functional Test: A electrical test of an entire assembly that stimulates the intended function of the product.
  52. Glass Transition Temperature: The temperature at which a polymer changes from a hard and relatively brittle condition to a viscous or rubbery condition. This transition generally occurs over a relatively narrow temperature range. It is not a phase transition. In this temperature region, many physical properties undergo significant and rapid changes. Some of those properties are hardness, brittleness, thermal expansion, and specific heat.
  53. Gull Wing Lead: A lead configuration typically used on small outline packages where leads bend and out. An end view of the package resembles a gull in flight.
  54. Icicles (Solder): A sharp point of solder that protrudes out of a solder joint, but does not make contact with another conductor. Icicles are not acceptable.
  55. In-Circuit Test: A electrical test of an assembly in which each component is tested individually, even though many electronic components are soldered to the board.
  56. Ionograph: An instrument designed to measure board cleanliness (the amount of ions present on a surface). It extracts ionizable materials from the surface of the part to be measured and records the rate of extraction and the quantity.
  57. JEDEC: Joint Electronic Devices Engineering Council.
  58. J-Lead: A lead configuration typically used on plastic chip carrier packages which have leads that are bent underneath the package body. A side view of the formed lead resembles the shape of the letter “J”.
  59. Known Good Die: Semiconductor die that has been tested and is known to function to specification.
  60. Laminar Wave: A smoothly flowing solder wave with no turbulence.
  61. Land: A portion of a conductive pattern usually, but not exclusively, used for the connection, or attachment, or both of components. (Also called a “pad”).
  62. Land Pattern: Component mounting sites located on the substrate that is intended for the interconnection of a compatible Surface Mount Component. Land patterns are also referred to as “lands” or “pads”.
  63. LCC: A nonpreferred term for “leadless ceramic chip carrier”.
  64. LCCC (Leadless Ceramic Chip Carrier): A ceramic, hermetically-sealed, integrated circuit (IC) package commonly used for military applications. The package has Metallized castellations on four sides for interconnecting to the substrate. (Also known as LCC).
  65. Leaching: The dissolution of a metal coating, such as silver and gold, into liquid solder. Nickel barrier interplating is used to prevent leaching. Also known as scavenging.
  66. Lead Configuration: The solid formed conductors that extend from a component and serve as a, mechanical and electrical connection that is readily formed to a desired configuration. The gull wing and J-lead are the most common surface mount lead configurations. Less common are butt leads formed by cutting standard DIP package leads at the knee.
  67. Lead Pitch: The distance between successive centers of the leads of a component package.
  68. Legend: Letters, numbers, symbols, and/or patterns on the PCB that are used to identify component locations and orientation for aid in assembly and rework / repair operations.
  69. Manhattan Effect: A solder open condition during reflow in which chip resistors and capacitor resemble a draw bridge.
  70. Mass Lamination: The simultaneous lamination of a number of pre-etched, multiple image, C-stage panels or sheets, sandwiched between layers of prepeg (B-stage) and copper foil.
  71. Mealing: A condition at the interface of the conformal coating and base material, in the form of discrete spots or patches, which reveals a separation of the conformal coating from the surface of the printed board (PCB), or from the surfaces of attached components, or from both.
  72. Measling: An internal condition that occurs in laminated base material in which the glass fibers are separated from the resin at the weave intersection. This condition manifests itself in the form of discrete white spots or “crosses” below the surface of the base material, and is usually related to the thermally induced stress.
  73. MELF: A metal electrode leadless face surface mount device that is round, cylindrical passive component with a metallic cap termination located at each end.
  74. Metallization: A metallic deposited on substrates and component terminations by itself, or over a base metal, to enable electrical and mechanical interconnections.
  75. Multichip Module (MCM): A circuit comprised of two or more silicon devices bonded directly to a substrate by wire bond, TAB, or flip chip.
  76. Multilayer Board: A Printed Wiring Board (PWB/PCB) that uses more than two layers for conductor routing. Internal layers are connected to the outer layers by way of plated via holes.
  77. Neutralizer: An alkaline chemical added to water to improve its ability to dissolve organic acid flux residue.
  78. No-Clean Soldering: A soldering process that uses a specially formulatedsolder paste that does not require the residues to be cleaned after solderprocessing.
  79. Node: An electrical junction connection two or more component terminations.
  80. Nonwetting: A condition whereby a surface has contacted molten solder, but has had part or none of the solder adhere to it. Nonwetting is recognized by the fact that the bare base metal is visible. It is usually caused by the presence of contamination on the surface to be soldered.
  81. Omegameter: An instrument used to measure board cleanliness (ionic residues on the surface of PCB assemblies). The measurement is taken by immersing the assembly into a predetermined volume of a water-alcohol mixture with a known high resistivity. The instrument records and measures the drop of resistivity caused by ionic residue over a specified period of time.
  82. Ounces of Copper: This refers to the thickness of copper foil on the surface of the laminate: ½ ounce copper, 1 ounce copper, and 2 ounce copper are common thickness. One ounce copper foil

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